Recently, technology scaling (e.g., to sub-100 nm dimensions) has resulted in relatively large random process variations that are incorporated into circuits and, particularly, has resulted in relatively large across chip variations in memory devices, e.g., sensing circuits. To compensate for these variations, sensing circuits typically operate with delays incorporated into the timing of the circuit, which degrades performance.
For example, in a Content Addressable Memory (CAM) each word is associated with a matchline that is precharged at the beginning of the cycle and discharged during the evaluation portion of the cycle if, and only if, the contents of the word mismatches the contents of the input search lines. Consequently the cycle time of the CAM, i.e., the fastest time (at a particular voltage and temperature) that this matching operation can be reliably repeated, is dependent on the precharge time, the evaluation (comparison) time and the time it takes to latch and propagate the results. To allow for statistical variations in manufacturing, each time portion of the overall operation must be carefully designed. Matchline precharge time is determined by generating a global precharge signal applied to a dummy matchline for a precharge time plus a fixed logic delay. Consequently, the precharge time for each matchline is globally fixed with no ability to adjust for precharge time variations from matchline to matchline. This precharge time also has no ability to sense and compensate for variable metal resistance and capacitance thereby forcing the designer to overdesign the various elements.